Various integrating filter circuits suited for incorporation into IC devices have been developed. Conventionally, these integrating filter circuits have utilized an integrating circuit comprised of transconductance circuits and capacitors, and a feedback technique for causing a desired filtering characteristic.
In a physical embodiment of the integrating filter circuit the integrating characteristic usually deviates from an ideal integrating characteristic. Such a deviation largely affects the integrating filter characteristic of the circuit. Thus it has been tried to bring the integration characteristic of integrating circuits close to the ideal integration characteristic by operating the integrating circuits with a fully differential circuit configuration. In such a differential circuit configuration, a common feedback technique is required to stabilize a differential operation.
FIG. 1 shows an example of such conventional integrating filter circuit utilizing the fully differential circuit configuration and the common feedback technique.
In FIG. 1, a capacitor C1 is connected in a transconductance circuit 10 consisting of a differential circuit 10A formed by transistors Q1 and Q2. The emitters of the transistors Q1 and Q2 are connected together, and then the common emitter node connected to a current source I1. The bases of the transistors Q1 and Q2 are coupled to input terminals IN for receiving an input signal. The collectors of the transistors Q1 and Q2 thus operate as current output ends. The collectors of the transistors Q1 and Q2 are connected not only to the collectors of transistors Q3 and Q4, but also to the bases of transistors Q6 and Q7. The transistors Q3, Q4, Q6 and Q7 construct a variable current source 10B as described later. The transistors Q6 and Q7 are arranged in an emitter-follower circuit configuration with current sources I2 and I3 connected to their emitters, respectively. The emitters of the transistors Q6 and Q7 are connected together through two series resistors R1 and R2 with a same resistance value.
The connecting node 10C of the resistors R1 and R2 is coupled to one input of a comparison circuit 20 comprised of transistors Q8 and Q9 which are arranged in a differential circuit configuration with a current source I4. For example, the voltage on the connecting node 10C, which represents an intermediate voltage Vi of the outputs of the differential circuit voltage, is applied to the base of the transistor Q8. The other input of the comparison circuit 20, i.e., the base of the other transistor Q9 is coupled to a source of the reference voltage Vref. Thus the intermediate voltage Vi of the outputs of the transconductance circuit 10 is compared with the reference voltage Vref at the comparison circuit 20.
A current resulted from the comparison in the comparison circuit 20 is applied to an integrating capacitor C2 which is connected to the collector of the transistor Q9. Thus an integrated voltage resulting from the integration by the integrating capacitor C2 is fed back to the transconductance circuit 10 through the transistors Q3 and Q4 of the variable current source 10B. As a result, the operating point of the transconductance circuit 10, i.e., the intermediate voltage Vi is stabilized by the common feedback operation via the connecting node 10C of the resistors R1 and R2 in the variable current source 10B, the comparison circuit 20 and the integrating capacitor C2.
The transfer function G(S) of the transconductance circuit 10 to collector voltage for this common feedback reference voltage Vref is expressed by the following Equation: ##EQU1##
In this Equation 1, gm1 and gm2 represent transconductances of the comparison circuit 20 consisting of the transistors Q8 and Q9 and the transconductance circuit 10 comprised of the transistors Q1 and Q2. .gamma..sub.0 also represents the parallel resistance of the output resistances of the transistors Q1 and Q3, or the transistors Q2 and Q4. S also represents a complex frequency.
As clearly seen from the above Equation 1, the transconductance circuit 10 is stable because the "pole" is in the left half field of S plane when the characteristic is represented on the polar coordinates. Further, as the capacitor C1 is connected between the collectors of the transistors Q1 and Q2, the capacitor C1 acts as equally as a circuit arrangement where two capacitors each having capacitance twice as the capacitance of the capacitor C1 are connected between the collectors of the transistors Q1 and Q2 and the ground potential source GND, respectively. Accordingly, the capacitor C1 have achieved a required capacitance for the transconductance circuit 10 with a small capacitor. Thus the circuit as shown in FIG. 1 is suited for fabricating on IC devices because IC devices are generally inadequate to fabricate thereon a large capacitor.
Thus, the integration filter circuit shown in FIG. 1 has such merits as it is stable and needed capacitance can be made small.
However, there still remains a large problem for implementing such transconductance circuit 10 on IC devices. That is, in physical IC devices parasitic capacitances inevitably exist around both ends of the capacitor C1 due to actual wiring conductors for coupling the capacitor C1 in the IC device. Therefore, when considering the parasitic capacitance Cp, the transfer function G(S) represented by the Equation 1 is changed to the following Equation: ##EQU2##
As seen from the Equation 2, the term of the parallel resistance .gamma..sub.0 is eliminated. This is because that the parallel resistance .gamma..sub.0, the complex frequency S and the parasitic capacitance Cp have a relation represented by following Equation: ##EQU3##
From the Equation 2, the gain G(j.omega.) becomes as follows: ##EQU4##
As easily seen from this Equation 4, the gain G(j.omega.) becomes not only infinite but also unstable when the .omega. is given by following Equation: EQU .omega.=[(gm1.multidot.gm2)/C2.multidot.Cp].sup.1/2 ( 5)
because the denominator of the Equation 4 becomes zero in the condition given by the Equation 5 and the gain G(j.omega.) shall go to infinity.
In the above case, if there exists a certain noise in the circuit, the noise is amplified so as to cause an abnormal oscillation in the circuit.
In other words, the reason for the circuit being unstable is due to that the denominator of Equation 2 has a quadratic form as to the complex frequency S. To prevent such an oscillation in the circuit, it is required that the integrating capacitor C2 is sufficiently large and further a resistor is connected to the integrating capacitor C2 in series. Therefore, even when the capacitor C1 could be made small, the integrating capacitor C2 still must be large. Thus devices implementing the conventional integrating filter circuit are difficult to reduced their size due to the problem of the requirement of the large capacitance for the integrating capacitor C2.
As described above, the conventional integrating filter circuit has such a defect that the common feedback operation becomes unstable by parasitic capacitances, and that the circuit is apt to oscillate. That is, when tried to prevent the defect, the merit of the reduction of the size of the capacitor C1 is hidden by the requirement of the large capacitance for the integrating capacitor C2.